U.S. Pat. No. 8,617,927 teaches a method of mounting electronic dice or chips into an electroformed heat spreader. Of course, the dice or chips either need to be interconnected with each other or connected to pins or connectors associated with the packaging material used to support or house the the dies or chips and their heat sinks (also called heat spreaders herein).
Wire bonds have been used in the prior art for both connecting contacts on a chip to the packaging it which it resides in use and also for chip to chip connections when multiple chips reside in a single package. Wire bonds, while seemingly small, with the continued tend for smaller and smaller device geometries, the wire bonds now are so large compared with the device geometries of modern integrated chips (ICs) that their size can make it difficult to couple modern ICs either with pins in the packaging in which the ICs reside or with neighboring ICs when multiple ICs are packaged together. This patent introduces a new technology which effectively replaces prior art wirebonding techniques with a new die to package and die to die interconnects which may be conveniently suspended over electrically conductive surfaces such as integrated heat sinks (or heat spreaders) which may be included in the packaging. The new technology is particularly suitable for wafer-level integration and wafer-level processing, which enables parallel interconnection of a multitude of chips at the wafer scale.
U.S. Pat. No. 5,198,385 describes the photolithographic formation of die-to-package airbridge in a semiconductor device, and focuses on single ceramic package integration. Advanced wafer-level packaging technologies that address thermal, electrical, and mechanical performance are now needed to develop low-cost IC packages. This patent introduces a new technology that enables integration of die-to-package and die-to-die interconnects over heat spreaders surrounding the dice, and embedded at the wafer level